Q1 – Which of the following statements is/are NOT CORRECT about NUMA?
(a) LOAD and STORE instructions are used to access remote memory.
(b) There is a single address space visible to all CPU.
(c) Access to local memory is slower than access to remote memory.
(d) When the access time to remote memory is hidden, the system is called NC-NUMA.
(e) IN CC-NUMA, coherent caches are present.
Choose the correct answer from the options given below:
(a) and (c) only
(b) and (d) only
(a) and (e) only
(c) and (d) only
(UGC NET DEC 2023)
Ans – (4)
Explanation – NUMA is an acronym for Non-Uniform Memory Access indicating memory architecture to fit multiprocessor systems where each CPU has its own little local memory, but can always access memory in possession of other processors. However, remote memory accesses are slower than local memory accesses.
In classic Symmetric Multiprocessing systems, all processors accessed a common pool of memory, but this could lead to congestion and significantly reduce performance. NUMA improved this by partitioning memory onto processors. The operating system always tried to keep together processes and data that behaved like hot spots, therefore reducing remote memory access.
Types of NUMA
CC-NUMA (Cache-Coherent NUMA) – This works by maintaining cache coherence: therefore, all CPUs see the changes in memory.
NC-NUMA (Non-Cache-Coherent NUMA) – Does not maintain cache coherence; rather, the software must manage it.
Option (a) – In NUMA, CPUs can access both local and remote memory using standard LOAD and STORE instructions.
Option (b) – NUMA maintains a shared address space such that any CPU can access memory; however, access times are varied.
Option (c) – Wrong, because local memory is faster.
Option (d) – Wrong, because there is no hidden access time here.
Option (e) – (Cache-Coherent NUMA ) uses cache coherence mechanisms to keep data consistent among different processors.
Q2 – A system bus in which each data item is transferred during a time slice known in advance to both units source and destination is called:
MIMD
DMA
asynchronous bus
synchronous bus
(UGC NET DEC 2023)
Ans – (4)
Explanation – A bus is that interconnecting wire system, operating within the boundaries of a computer, used for data transfer between various units such as CPU, memory, and I/O devices.
Synchronous buses are working with a fixed time slice (i.e., a clock cycle) where the data transfer is staged by the sources and destinations at fixed times known in advance or make some arrangement memorable to both the parties in concern.
In sync with a common clock signal, it coordinates along that same bus for all devices.
Other options –
MIMD (Multiple Instruction Multiple Data) is a computer architecture that utilizes multiple processors to carry out different instructions simultaneously on various data. It doesn’t relate to bus timing.
DMA (Direct Memory Access) means transferring data from memory or to external devices without the involvement of the microprocessor. It does not refer to any style of bus.
Asynchronous Bus is distinguished by time slices whose values do not always exist but is determined using handshake signals that synchronize each other data transfer.
Q3 – Which of the following circuit is used to store one bit of data ?
Encoder
Decoder
Flip-Flop
Register
(UGC NET DEC 2023)
Ans – (3)
Explanation – A Flip-Flop is a sequential circuit that is used to store one bit of data. It has two stable states (0 or 1) and can be used as a basic memory unit in digital circuits. Flip-flops are widely used in registers, counters, and memory units.
Q4 – In most general case, the computer needs to process each instruction with the following sequence of steps:
(A) Calculate the effective address
(B) Execute the instruction
(C) Fetch the instruction from memory
(D) Fetch the operand from memory
(E) Decode the instruction
Choose the correct answer from the options given below:
(A), (B), (C), (D), (E)
(A), (B), (C), (E), (D)
(C), (E), (A), (D), (B)
(C), (E), (D), (A), (B)
(UGC NET DEC 2023)
Ans – (3)
Explanation – Considering the most general case, the proper order of steps for processing an instruction is as follows –
(C) Fetch the instruction from memory – Instruction is brought from memory.
(E) Decode the instruction – Determine the meaning of the instruction that needs to perform an operation.
(A) Calculate the effective address – The effective address is calculated if the instruction requires memory access.
(D) Fetch the operand from memory – The operand is brought from memory (again, if needed).
(B) Execute the instruction – The CPU executes the operation dictated by that instruction.
Hence the right choice is option 3.
Q5 – Match List – I with List – II.
List – I
(A) SZA
(B) SKI
(C) SNA
(D) ISZ
List – II
(I) Increment M and skip it zero
(II) Skip if AC is negative
(III) Skip if input flag is on
(IV) Skip if AC is Zero
Choose the correct answer from the options given below:
(A)-(II), (B)-(IV), (C)-(I), (D)-(III)
(A)-(IV), (B)-(III), (C)-(II), (D)-(I)
(A)-(IV), (B)-(II), (C)-(I), (D)-(III)
(A)-(III), (B)-(IV), (C)-(II), (D)-(I)
(UGC NET DEC 2023)
Ans – (2)
Explanation – (A) SZA implies (IV) Skip if AC is Zero.
If the AC register has a value equal to 0, then the next instruction will be skipped. In case AC is not equal to zero, then the program will go down to mean execution.
(B) SKI implies (III) Skip if the Input Flag is set On.
Processor will skip the next instruction if the input flag is set (that is, an input device has data ready).
(C) SNA implies (II) Skip if the Accumulator (for AC) is Negative.
If the value contained in the AC register is negative, then skip the next instruction.
(D) ISZ implies (I) Increment Memory (M) And Skip If Zero.
This instruction increments the value stored in a memory location M. If after incrementing M becomes 0, the program skips the next instruction.
Q6 – The average time required to search a storage location in memory and obtain its contents is called:
Access time
Latency time
Response time
Reading time
(UGC NET DEC 2023)
Ans – (1)
Explanation – Access time is defined as the average time taken for a given storage location in memory to be located and retrieve its contents.
This consists of memory latency (the time period consumed to access the memory location area) and transfer time (the time needed for reading data).
Access time is an important evaluation factor for accessing a memory system performance.
Why not Other Options?
Latency time – It normally refers to just the time before the transfer of data begins. It does not include the whole process of retrieval.
Response time – Commonly used in computing to refer to the complete time taken for any system to respond to the given request.
Reading time – This is not a commonly used standard technical term for memory retrieval speed.
Q7 – The microoperation which divides a signed binary number by 2 is:
Circular shift
Logical shift
Arithmetic shift right
Arithmetic shift left
(UGC NET DEC 2023)
Ans – (2)
Explanation – When it comes to signed binary division by 2, the thing to ensure is that the sign of the binary number (positive or negative) is preserved. This is done through an arithmetic right shift (ASR), in which all bits including the sign bit are shifted to the right.
Binary Representation – 1111 1100 (-4)
Arithmetic Shift Right (ASR) – 1111 1110 (Correct result is -2)
Q8 – Identify the code sequence :
1010
1011
1001
1000
BCD
Excess-3
Gray
Excess-3 gray
(UGC NET DEC 2023)
Ans – (3)
Explanation – Gray code is a binary numeral system where two successive values differ in only one bit.
1010 -> 1011 last bit change (12 -> 13)
1011 -> 1001 Third bit change (13 -> 14)
1001 -> 1000 last bit change (14 -> 15)
Excess-3 Gray Code is a Gray code version of Excess-3, where each successive number differs by only one bit.
1010 -> 1011 last bit change (9 -> 10)
1011 -> 1001 Third bit change (10 -> 11)
1001 -> 1000 last bit change (11 -> 12)
But Excess-3 Gray code is not used in any manner in any operation. UGC just planted this, just to confuse you.
Other options –
BCD is a binary representation of decimal numbers where each digit is represented separately in 4 bits, and yes, the given code sequence has also 4 bits, but it is not in any type of sequence. 1010 is 10, 1011 is 11, 1001 is 9 and 1000 is 8.
Excess-3 is a modified BCD code where each BCD digit is incremented by 3.
Q9 – Three address codes can be represented in special structures known as:
(A) Quadruples
(B) Triples
(C) Patterns
(D) Indirect Triples
Choose the correct answer from the options given below :
(A) and (B) Only
(A), (B) and (D) Only
(B) and (C) Only
(B), (C) and (D) Only
(UGC NET DEC 2023)
Ans – (2)
Explanation – Three-address codes can be represented using certain structures that help in organizing an intermediate representation of code inside a compiler. The structures are named Quadruples, Triples, and Indirect Triples.
(A) Quadruples – This has four fields operator, argument1, argument2, and result, which helps in organizing expressions and statements in a neat and efficient format.
(B) Triples – Unlike quadruples, this does not provide a separate field for storing the result. Instead, the reference to the results uses indices.
(D) Indirect Triples – A variation of the triples is one in which pointers are used to reference statements, easing the process of reordering the code.
